integrated circuit systems, inc. general description features ics9169a-70 block diagram frequency generator for workstation systems 9169a-70 rev b 2/14/01 pin configuration 32-pin soic ? 9 pci outputs selectable from 30 to 66.6mhz 3 scsi outputs, selectable from 10 to 80mhz 500ps skew window for all synchronous clock edges integrated buffer outputs drive up to 30pf loads 500ps output to output skew window buffers drive 30pf loads nominally 0.8v/ns skew rate 3.0v - 3.7vsupply range 32-pin soic package 48 mhz clock for usb support and 24 mhz clock for fd the ics9169a-70 is a low-cost frequency generator designed specifically for workstation or pc system clocks. the integrated buffer minimizes skew and provides all the clocks required. a 14.318 mhz xtal oscillator provides the reference clock to generate standard pentium frequencies. the cpu clock makes gradual frequency transitions without violating the pll timing of internal microprocessor clock multipliers. ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9169a-70 pin descriptions r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 11 d d vr w p. s r e f f u b t u p t u o d n a l l p , c i g o l r o f r e w o p 21 xn i s i h t . t u p n i y c n e u q e r f e c n e r e f e r l a n r e t x e r o l a t x k c a b d e e f d n a e c n a t i c a p a c d a o l l a t x s e d u l c n i t u p n i 8 1 8 1 3 . 4 1 y l l a n i m o n , l a t s y r c z h m 6 1 - 2 1 a r o f s a i b . z h m 32 xt u o d a o l l a t x s e d u l c n i h c i h w t u p t u o l a t x . e c n a t i c a p a c 4 2 , 3 2 , 0 2 , 4 1 , 3 1 , 0 1 , 9 , 6 , 5) 8 : 0 ( i c pt u os t u p t u o k c o l c i c p 5 2 , 2 2 , 9 1 , 1 1 , 7 , 4d n gr w p. s r e f f u b t u p t u o d n a l l p , c i g o l r o f d n u o r g 1 2 , 2 1 , 83 d d vr w ps t u p t u o k c o l c i c p r o f r e w o p 7 1 , 6 1 , 5 1a ) 2 : 0 ( s fn i . e v o b a e l b a t e e s . s n i p t c e l e s r e i l p i t l u m y c n e u q e r f . s e c i v e d p u l l u p l a n r e t n i e v a h s t u p n i e s e h t 9 22 d d vr w ps t u p t u o k c o l c i s c s r o f r e w o p 6 2 , 7 2 , 8 2) 2 : 0 ( i s c st u os t u p t u o k c o l c i s c s 8 1 , 0 3 , 1 3b ) 2 : 0 ( s fn i t x e n e l b a t e e s . s n i p t c e l e s r e i l p i t l u m y c n e u q e r f s e c i v e d p u l l u p l a n r e t n i e v a h s t u p n i e s e h t . e g a p 2 30 f e rt u o r o r o t a l l i c s o l a t s y r c e h t f o y p o c d e r e f f u b a s i f e r . z h m 8 1 8 1 3 . 4 1 y l l a n i m o n , k c o l c t u p n i e c n e r e f e r note: x1, x2 contain iternal 18pf crystal load cap. intended to have external load caps of 15 to 18pf required for nominal crystal of 17 to 18pf crystal total load.
3 ics9169a-70 b 2 s fb 1 s fb 0 s f t e g r a t z h m l a u t c a z h m f e r z h m 000 4 24 28 1 3 . 4 1 001 8 47 0 . 8 48 1 3 . 4 1 010 0 12 0 . 0 18 1 3 . 4 1 0110 25 0 . 0 28 1 3 . 4 1 100 0 49 0 . 0 48 1 3 . 4 1 10 1 0 51 1 . 0 58 1 3 . 4 1 110 0 64 1 . 0 68 1 3 . 4 1 111 0 88 1 . 0 88 1 3 . 4 1 a 2 s fa 1 s fa 0 s f t e g r a t z h m l a u t c a z h m f e r z h m 000 e t a t s i r te t a t s i r te t a t s i r t 001 2 / f e r2 / f e rf e r 010 0 37 0 . 0 38 1 3 . 4 1 011 3 . 3 37 2 . 3 38 1 3 . 4 1 100 0 51 1 . 0 58 1 3 . 4 1 10 1 5 59 8 . 4 58 1 3 . 4 1 110 0 64 1 . 0 68 1 3 . 4 1 111 6 . 6 63 6 . 6 68 1 3 . 4 1 scsi outputs: scsi(0:2) (assume divide by 2 from vco) pci outputs: pci (0:8) (assume divide by 2 from vco) vdd = 3.310%, ta = 0 to 70c crystal = 14.31818mhz note: when fs(0:2)a is 000 or 001, the tristate and test modes applies to all outputs for ref, pci, and scsi outputs. note: 1. in test mode, each pll is bypassed. the clock signal at x1 (externally driven clock or the crystal) is applied to the divider circuits. a 2 s fa 1 s fa 0 s fi c pi s c s f e r 000 e t a t s i r te t a t s i r te t a t s i r t 001 2 / f e r 1 2 / f e r 1 f e r 1
4 ics9169a-70 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - ref t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -14 ma 2.4 2.9 v output low voltage v ol1 i o l = 11 ma 0.3 0.4 v output high current i oh1 v o h = 2.0 v -43.0 23.0 ma output low current i ol1 v ol = 0.8 v 20.0 31.0 ma rise time t r5 1 v o l = 0.8 v, v o h = 2.4 v 0.7 1.5 ns fall time t f5 1 v o h = 2.4 v, v ol = 0.8 v 0.6 1.5 ns duty cycle d t5 1 v t = 1.5 v 405360% jitter t j1s5 1 v t = 1.5 v - 182 400 ps t jabs5 1 v t = 1.5 v -700 - 700 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; su pp l y volta g e v dd = 3.3 v +/-10% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2.0 - - v input low voltage v il --0.9v input high current i ih1 v in = v dd -5 0.2 5 ma input low current i il1 v in = 0 v -20 -50.0 - ma supply current i dd c l = 0 pf; select @ 66m 50 110 ma input frequency f i v dd = 3.3 v; 14.318 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27.0 36.0 45.0 pf transition time 1 t trans to 1st crossing of target freq. 0.136 2.0 ms settling time 1 t s from 1st crossing to 1% target freq. 63.0 600 s clock overshoot 1 t s h 1.7 4.0 mhz clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3ms 1 guarenteed by design, not 100% tested in production.
5 ics9169a-70 electrical characteristics - scsi t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -14 ma 2.4 2.9 v output low voltage v ol1 i ol = 11 ma 0.3 0.4 v output high current i oh1 v oh = 2.0 v -43.0 23.0 ma output low current i ol1 v ol = 0.8 v 20.0 31.0 ma ris e time t r5 1 v ol = 0.8 v, v oh = 2.4 v 0.7 1.5 ns fall time t f5 1 v oh = 2.4 v, v ol = 0.8 v 0.6 1.5 ns duty cycle d t5 1 v t = 1.5 v 45 50 55 % skew (window) t sk1 1 v t = 1.4 v -250 - 250 ps jitter t j1s5 1 v t = 1.5 v; r s= 33; (10 to 24 mhz clocks ) - 200 300 ps t j1s5 1 v t = 1.5 v; r s= 33; (40 to 80 mhz clocks ) - 90 150 ps t jabs5 1 v t = 1.5 v; r s= 33; (10 to 24 mhz clocks ) -700 - 700 t jabs5 1 v t = 1.5 v; r s= 33; (40 to 80 mhz clocks ) -400 - 400 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-10%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -14 ma 2.4 2.9 v output low voltage v ol1 i ol = 11 ma 0.3 0.4 v output high current i oh1 v oh = 2.0 v -43.0 23.0 ma output low current i ol1 v ol = 0.8 v 20.0 31.0 ma ris e time t r1 1 v ol = 0.8 v, v oh = 2.4 v 0.8 1.5 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.8 v 0.9 1.5 ns duty cycle d t1 1 v t = 1.4 v 45.0 51.0 55.0 % skew (window) t sk1 1 v t = 1.4 v -250 250 ps jitter t j1s1 1 v t = 1.5 v; r s= 33 88 150 ps t jabs1 1 v t = 1.5 v; r s= 33 -300 300 ps 1 guarenteed by design, not 100% tested in production.
6 ics9169a-70 general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. notes: 1 all clock outputs should have series terminating resistor. not shown in all places to improve readibility of diagram 2 optional emi capacitor should be used on all cpu, sdram, and pci outputs. 3 optional crystal load capacitors are recommended. capacitor values: c1, c2 : crystal load values determined by user all unmarked capacitors are 0.01f ceramic
7 ics9169a-70 soic package ordering information ICS9169AM-70 pattern number (2 or 3 digit number for parts with rom code patterns) package type m=soic device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx m - ppp t n u o c d a e ll 2 3 l n o s n e m i d4 0 8 . ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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